Liquid crystal displays (LCDs) typically include an array of isolation or switching devices such as TFTs or diodes. Thin film transistors (TFTs) formed from deposited semiconductors such as amorphous silicon (a-Si) alloys are ideally suited for such applications because they exhibit a high dark resistivity and, therefore, have low OFF state currents. The leakage currents are low so that high on-to-off current ratios are made possible for effectively isolating non-addressed array pixels from the pixels being addressed. Current flow through TFTs between the source and drain is controlled by the application of voltage to the gate electrode. Voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted.
The source and drain electrodes in conventional TFT arrays are typically deposited and patterned on a substrate by way of either flat panel steppers or large area scanning projection aligners in order to define a channel length and width between the source and drain. Large area scanning projection aligners which use a single large area mask typically cost about half as much as flat panel steppers, and have about twice the manufacturing throughput as the steppers. Conventional scanning projection aligners typically have a resolution of from about 4 to 6 .mu.m while conventional flat panel steppers typically have a resolution of from about 3 to 4 .mu.m. In consideration of cost and manufacturing throughput, it is clear that it would be desirable to utilize scanning projection aligners as opposed to flat panel steppers so as to decrease manufacturing costs and increase production throughput.
TFT channel lengths smaller than those achievable with certain scanning projection aligners are often desirable for reasons to be discussed below. Typically, TFT source-drain channel lengths of about 6 .mu.m can be obtained with some scanning projection aligners. However, it is often desirable to reduce channel lengths to less than 6 .mu.m. For yield purposes, however, channel length design often exceeds resolution of the aligners by a factor of about 1.5 to 2.
The resulting channel length of a TFT is typically larger or longer than the feature size of the aligner used due to overetching of the source and drain. In the case of Mo source-drain metal, for example, the overetch is typically about 1 .mu.m so that a designed channel length of 4 .mu.m ends up as a post-processing TFT channel length of about 6 .mu.m. As a result of this, the channel width must be increased in order to maintain the same ON current because the TFT ON current is proportional to W/L where "W" is the channel width and "L" is the channel length. Accordingly, there exists a need in the art for a thin film transistor (and method of manufacturing same) having a channel length smaller than that allowed by the feature size or resolution of the equipment used to manufacture the TFT (given a particular yield requirement) so that, for example, about a 4 .mu.m channel length or less can be achieved using low-cost equipment such as scanning projection aligners (instead of flat panel steppers). It is desirable to perform as few manufacturing steps as possible in making a TFT and corresponding LCD.
Smaller TFT channel lengths are desirable for the following reasons. Pixel voltage shift .DELTA.V.sub.p in thin film transistor LCDs after switching off the gate electrode is proportional to the gate-source capacitance (C.sub.gs) of the thin film transistor. .DELTA.V.sub.p can cause flicker, image retention, and gray level non-uniformity in liquid crystal display operation. An effective way to reduce C.sub.gs (i.e. parasitic or gate-source capacitance) is by shortening the channel length of the TFT. When a channel length is reduced, the channel width "W" can be reduced proportionally so as to decrease C.sub.gs because C.sub.gs is proportional to the channel width. Such reduction in channel width is permitted while the same I.sub.ON of the TFT is maintained due to the reduced channel length. This reduction in channel width is a major contributor in reducing C.sub.gs.
FIG. 1 is a side elevational cross sectional view of prior art linear thin film transistor (TFT) 1. See U.S. Pat. No. 5,055,899. A plurality of TFTs 1 are typically arranged on transparent insulating substrate 3 in the form of a matrix array in AMLCD applications. Each TFT 1 includes gate electrode 5 connected to a gate line (not shown) extending in the row direction, drain electrode 7 connected to a drain line (not shown) extending the column direction, and source electrode 9 connected to transparent pixel electrode 11 independently formed in an area surrounded by the gate and drain lines. Pixel electrode 11 operates in conjunction with an opposing electrode on the other side of the liquid crystal (LC) layer (not shown) so as to selectively drive the pixel enabling the respective polarizers to transmit or absorb light rays in order to create an image for the viewer. A TFT electrode, to which a data signal is supplied, will be referred to hereinafter as a drain electrode.
More specifically, gate electrode 5 is formed on clear substrate 3. Gate insulating film 13, made of silicon oxide or silicon nitride, for example, is formed both on substrate 3 and on the upper surface of gate electrode 5. Semiconductor film 15, consisting of amorphous silicon (a-Si), for example, is stacked on gate insulating film 13 above gate 5. Drain and source electrodes 7 and 9 respectively are formed on semiconductor film 15. The linear shaped source and drain electrodes are separated from one another by a predetermined distance forming channel length 17. Drain and source electrodes 7 and 9 respectively utilize contact layers 7a and 9a, and source-drain metal layers 7b and 9b, and are electrically connected to semiconductor film 15.
Unfortunately, when prior art TFT 1 is manufactured using, for example, a conventional scanning projection aligner to position the source and drain electrodes on substrate 3, the resulting channel length 17 of TFT 1 cannot be made as small as often desired thereby resulting in an undesirably high parasitic capacitance (C.sub.gs). High parasitic capacitance values for TFTs are undesirable as set forth above because they tend to cause pixel flickering, image retention, and gray scale non-uniformity. As the parasitic capacitance of a TFT is decreased, the pixel voltage shift when the gate is switched off becomes smaller. As the pixel voltage shift decreases, it becomes easier to compensate the top plate voltage to eliminate DC components for all gray levels across the entire display area.
Flickering results from a small DC component across the pixel electrodes spanning the liquid crystal layer. Pure AC voltage across the electrodes is ideal. By reducing the parasitic capacitance, the DC component across the pixel electrodes can be substantially eliminated or reduced thereby greatly reducing pixel flickering, electrochemical degradation, and image retention of the LC material.
In view of the above, it is apparent that there exists a need in the art for a liquid crystal display including a TFT array and method of making same using the least number of manufacturing steps as possible, wherein the TFTs in the array have reduced parasitic capacitances and are cost effective to manufacture. Such TFTs are achievable in accordance with this invention by reducing the obtainable TFT channel lengths so as to decrease parasitic capacitance values in order to reduce flickering, image retention, and gray scale non-uniformity of the display. It would also be desirable if TFT channel lengths smaller than those allowed by the feature size of the manufacturing equipment and compatible with high yield requirements could be obtained so as to reduce costs.
It is a purpose of this invention to fulfill the above-described needs, as well as other needs in the art which will become more apparent to the skilled artisan once given the following disclosure.
Above-identified U.S. Ser. No. 08/444,673 discloses one way in which to solve certain of the above-discussed problems in the prior art. While the '673 invention is an excellent solution to these problems in of itself, the invention(s) according to certain embodiments of this application offer alternative efficient solutions.